Technical Field
This disclosure relates to processor cache operation, and more particularly to cache management mechanisms.
Description of the Related Art
Modern processors use a number of cache memory hierarchies in an effort to expedite data retrieval from main memory. In particular, most all processor cores will have at least a level one (L1) cache that is proximal to the core. In many cases, and especially in multi-core designs, a processor will also have a level two (L2) cache, and in some cases a level three (L3) cache. The L2 and L3 caches are in many cases shared among the various processor cores. The multiple cache hierarchies allow a processing system to keep copies of data that is accessed frequently in the local faster cache memory hierarchy, rather than having to access main memory which is typically slower.
When a processor requests data or a program instruction that is not contained within a cache memory, a further request may be made to main memory for desired information. The processor may also request that the information be stored in the cache memory so that the information may subsequently be retrieved from the cache memory as opposed to main memory. Storing new information in a cache memory may be dependent upon available space within the cache memory. In cases where the cache memory is already storing its maximum number of cache lines, a line may need to be selected for removal (commonly referred to as “eviction”) from the cache memory. Once a previously stored cache line has been selected and evicted from the cache memory, a new cache line may be stored.